Memory-Mapped I/O is a well-known mechanism used by many processors, such as Intel® processors and Power PC® processors, among others, to access Input Output (I/O) devices. Through this mechanism, I/O device controls are mapped into a range of well-known addresses. Dynamic address translation mechanisms along with translation look aside buffers (TLB) are implemented in hardware to provide the mapping. I/O devices are accessed through regular load and store instructions by specifying addresses that correspond to I/O device controls.
zSeries® machines are based on the z/Architecture®. The z/Architecture® and its predecessors have traditionally used I/O channels to access I/O device controls and are not configured to directly support the memory-mapped I/O paradigm. pSeries® and iSeries® machines are based on the PowerPC® processor which uses the memory-mapped I/O paradigm.
The InfiniBand™ architecture defines an Input Output (I/O) networking standard that provides zero processor-copy data transfers, i.e., with no kernel involvement, between its I/O and Inter-Process Communication (IPC) clients, and uses hardware to provide highly reliable, fault tolerant communications. Interfaces that conform to the InfiniBand™ architecture standard may exhibit preferred capabilities and wide industry acceptance.
Therefore, what is needed in the art in order to provide greater interoperability with industry standard I/O devices, for the z/Series® architecture, is support for InfiniBand™ in the z/Architecture®.